During the integrated circuit (IC) design process, various components within an IC design are modeled and simulated so that the performance of those components can be verified against various design requirements before the IC is physically produced. If the modeled IC design does not perform as required, various parts of the IC design are modified, and the resulting IC design is again modeled and simulated. This process continues until a satisfactory IC design is obtained.
An interconnect model can also be used to model the cell timing (based on cell delay and interconnect delay) of a cell connected to an interconnect being modeled. There are many different interconnect models. One model, referred to as a pi model, is generated using moment-matching techniques based on information extracted from the physical layout of the IC design. The pi model can be obtained by moment-matching the first three moments of the driving point admittance of a more complex interconnect model extracted from the physical layout. The resulting pi model, which includes two capacitances connected by a resistance, can then be reduced to a lumped-capacitance model, which includes a single effective capacitance. Conversion from a pi model to a lumped-capacitance model typically involves using numeric methods. The lumped-capacitance model represents the driving point admittance of the interconnect model, which is in turn used to perform interconnect delay analysis.
In general, it is desirable that interconnect models represent the real-world performance of an interconnect as accurately as possible. More accurate interconnect models allow designers to more reliably detect design errors while also reducing the amount of overdesign (i.e., designing an IC more conservatively than is actually required, resulting in unneeded components or space or in decreased performance). However, the desire for more accurate interconnect models is balanced against the need to obtain an interconnect model within a reasonable amount of time. Generally, the more accurate the modeling technique, the more computationally intensive it is to obtain the model. Accordingly, less accurate models are often used in commercial applications because such models can be obtained significantly more quickly for complicated IC designs than more accurate models could be obtained. Since interconnect delay analysis is a necessary part of the IC design process, it is desirable to have techniques for obtaining the effective capacitance of an interconnect model that are both accurate and relatively simple to obtain.
Overview of Interconnect Models
FIG. 1 illustrates a generic interconnect model used to perform interconnect delay analysis in VDSM (Very Deep Sub-Micron) IC design processes. The model in FIG. 1 includes virtual source node 101 at which voltage V0(t) is applied as a stimulus to driver 110. Driver 110 represents a gate coupled to drive a signal on the interconnect represented by R(L)C network 120 (R(L)C refers to a network that includes one or more resistances R and one or more capacitances C, and that can, in some cases, include one or more optional inductances L).
The model includes driving point node 103. Voltage VDP(t) is measured between driving point node 103 and ground. Driving point node 103 is located between the output of driver 110 and the input to R(L)C network 120. Current IDP(t) flows from driver 110 to R(L)C network 120.
R(L)C network 120 models an interconnect as an R(L)C network without a DC (Direct Current) connection to ground. R(L)C network 120 includes N interconnect nodes (only one such interconnect node, interconnect node 105(k), is shown in the example of FIG. 1). Capacitance Ck couples interconnect node 105(k) to ground, and voltage Vk(t) is measured across capacitance Ck. Each other interconnect node (if any) in R(L)C network 120 is similarly coupled to ground by a respective capacitance across which a respective voltage is measured.
R(L)C network 120 can be obtained by extracting predicted electrical parasitics from the physical layout of an IC design. The model of FIG. 1 is characterized by its voltage transfer function, Hk(s)=Vk(s)/V0(s), and its driving point admittance Y(s), where Y(s)=IDP(s)/VDP(s). The driving point admittance represents the admittance of R(L)C network 120 as seen at driving point node 103. The model of FIG. 1 can be reduced to an Nth order model by matching the first N+1 moments of the driving point admittance Y(s). Such a reduction simplifies delay calculation, while preserving at least some of the accuracy of the representation of the driving point admittance Y(s).
The timing characteristics of cells in an IC design are typically characterized by a lumped capacitive load. However, such characterizations are typically too inaccurate to represent R(L)C network 120. At the same time, using the model of FIG. 1 to perform timing analysis may be undesirable, due the large amount of computation effort needed to analyze the model. To preserve at least some accuracy while reducing the computation effort, the model of FIG. 1 is typically reduced to an equivalent lumped-capacitance interconnect model like the one shown in FIG. 2.
FIG. 2 illustrates a lumped-capacitance interconnect model that is derived from the interconnect model shown in FIG. 1. The lumped-capacitance interconnect model is similar to the interconnect model of FIG. 1, but R(L)C network 120 has been replaced with Ceff. Ceff is the effective capacitance of R(L)C network 120. Current I(t) flows into Ceff, and voltage V(t) is measured across Ceff.
Ceff is an “effective” capacitance in that its value is selected so that the average current flowing through Ceff of FIG. 2 is equal to the average current flowing through driving point node 103 of FIG. 1. The average current (Iavg, shown in the equation below) flowing through Ceff equals the product of 1/T and the integral from t=0 to t=T of I(t)dt, which in turn equals the product of 1/T, Ceff, and V(T) (with V(0)=0). Time t=0 is the time at which ramp voltage V0(t) stimulus to driver 110 begins ramping up; t=T is the time at which ramp voltage V0(t) reaches its final value.
      I    avg    =                    1        T            ·                        ∫          0          T                ⁢                              I            ⁡                          (              t              )                                ⁢                                          ⁢                      ⅆ            t                                =                  1        T            ·              C        eff            ·              V        ⁡                  (          T          )                    The average current (IDPavg, shown in the equation below) through driving point node 103 equals the product of 1/T and the integral from t=0 to t=T of IDP(t)dt. This average current in turn equals the product of 1/T and the sum, from k=1 to N, of the product of Ck and Vk(T), with Vk(0)=0. N is the total number of interconnect nodes in R(L)C network 120 of FIG. 1.
      I    DPavg    =                    1        T            ·                        ∫          0          T                ⁢                                            I              DP                        ⁡                          (              t              )                                ⁢                                          ⁢                      ⅆ            t                                =                  1        T            ·                        ∑                      k            =            1                    N                ⁢                              C            k                    ·                                    V              k                        ⁡                          (              T              )                                          By equating Iavg with IDPavg, equation Eq. 1 in FIG. 2 is obtained.
Equation Eq. 1 is used to calculate the value of the effective capacitance, Ceff, for use in the lumped-capacitance interconnect model, from the characteristics of an interconnect model such as the one shown in FIG. 1. Equation Eq. 1 states that the product of Ceff and V(T) is equal to the sum, from k=1 to k=N, of the product of Ck and Vk(T) (as shown in FIG. 1). N is the total number of interconnect nodes in R(L)C network 120 of FIG. 1.
The equation Eq. 1 shown in FIG. 2 requires a numerical solution if N>1 and VDP(t) is not equal to V(t) (i.e., if the driving point voltage in FIG. 1 is not equal to the voltage across the effective capacitance Ceff in FIG. 2). V(T) depends on Ceff (i.e., V(T)=f(Ceff)). To solve Eq. 1 thus requires the use of numerical methods (e.g., trial and error, Newton-Raphson iteration, and the like). The use of numerical methods can undesirably increase the computation effort needed to calculate the value of Ceff. For example, faster processors, larger memories, and/or more computation time may be required to solve for Ceff than is desirable.